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PowerQUICC II Register Programming
1
Programmed into the E 2 PROM in addresses 0x0, 0x8, 0x10 & 0x18
Table 6-5. SIU Register Programming
Register
RMR
IMMR
SYPCR
BCR
Init
Value[hex]
0001
04700000
FFFFFFC3
100C0000
Description
Check-Stop Reset enabled.
Internal space @ 0x047000000
Software watchdog timer count - FFFF, Bus-monitor timing FF, PPC Bus-monitor -
Enabled, Local Bus-monitor - Enabled, S/W watch-dog - disabled, S/W watch-dog
(if enabled) causes reset, S/W watch-dog (if enabled) - prescaled.
Single PowerQUICC II, 1 wait-states on address tenure, No L2Cache, 1 clock hit
delay (when L2cache available), 1-level Pipeline depth, Extended transfer mode
enabled for PCC, Extended transfer mode disabled for Local Buses, Odd parity for
PPC & Local Buses, External Master delay enabled, Internal space responds as 64
bit slave for external master (not relevant for this application).
6.2.2
Memory Controller Register Programming
The memory controller on the MPC8272ADS is initialized to 100MHz operation, that is,
the registers’ programming is based on 100-MHz timing calculation. It also works for
slower bus speeds, but the timing must be optimized). The two possible initialization for
the memory controller are the following:
?
?
Flash SIMM is assigned to CS0 and E 2 PROM is assigned to CS4.
Flash SIMM is assigned to CS4 and E 2 PROM is assigned to CS0.
Both options are shown in Table 6-6 and Table 6-7, respectively.
Table 6-6. Memory Controller Initialization For 100MHz—Flash as Boot Device
Reg.
BR0
Device Type
SM73228XG1JHBG0 by
Bus
PPC
Init Value
[hex]
FF801801
Description
Base at FF800000, 32 bit port size, no parity,
Smart Modular Tech.
GPCM
SM73248XG2JHBG0 by
Smart Modular Tech.
SM73288XG4JHBG0 by
Smart Modular Tech.
FF001801
FE001801
Base at FF000000, 32 bit port size, no parity,
GPCM
Base at FE000000, 32 bit port size, no parity,
GPCM
OR0
SM73228XG1JHBG0 by
Smart Modular Tech.
SM73248XG2JHBG0 by
Smart Modular Tech.
SM73288XG4JHBG0 by
Smart Modular Tech.
FF800876
FF000876
FE000876
8MByte block size, CS early negate, 11 w.s.,
Timing relax
16MByte block size, CS early negate, 11 w.s.,
Timing relax
32MByte block size, CS early negate, 11 w.s.,
Timing relax
Chapter 6. Memory Map
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